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This invention relates generally to the field of hardware description languages. More particularly, this invention relates to a method of providing regular expression support for module iteration (instantiation) and interconnection in hardware description languages.
A hardware description language (HDL) is a computer language used to describe electronic circuits. The description can describe the circuit at a number of different levels. For example, a hardware description language can be used to describe the interconnection of modules, sub-modules, transistors, resisters, capacitors, etc. Hardware description languages can also be utilized to describe the logical operation of logic gates, flip-flops and the like in digital systems and to describe the transfer of vectors of information between registers.
One of the most popular hardware description languages is the IEEE standard Verilog(trademark). In this, and other HDLs, when multiple iterations of the same type of component (module) are used in a particular arrangement and interconnected with one another and/or other types of modules, an individual description of each module xe2x80x9cinstancexe2x80x9d of each module type is generated to represent the particular module instance and it""s interconnection. Manually generating each iteration of a particular module type can be quite tedious. So, the IEEE, in its current working draft of IEEE 1364 (draft 5) Verilog(trademark) proposal (See IEEE Proposed Standard 1364-2000 (Draft 5) xe2x80x9cIEEE Standard Hardware Description Language Based on the Verilog Hardware Description Languagexe2x80x9d, IEEE, Inc., New York, N.Y., USA, March, 2000, and xe2x80x9cIEEE Standard 1076-1993 IEEE VHDL Language Reference Manualxe2x80x9d, IEEE, Inc., New York, N.Y., USA, Jun. 6, 1994) proposes a standard technique using preprocessing at the interconnect level in a xe2x80x9cfor loopxe2x80x9d to achieve iteration and interconnection. The example provided in this proposal is repeated below as EXAMPLE 1 for convenience:
In this example, a module named smsxe2x80x9416b216t0 is to be instantiated and interconnected four times as the variable xe2x80x9cixe2x80x9d is iterated from values 0 through 4. Each of the lines following the first line represents a port on the module with signal names, as will be appreciated by those familiar with Verilog(trademark).
Unfortunately, xe2x80x9cfor loopsxe2x80x9d and xe2x80x9cgenerate loopsxe2x80x9d suffer from several disadvantages. The use of xe2x80x9cfor loopsxe2x80x9d in preprocessing was added as an extension to the Verilog language in response to the user community""s desire to provide a capability similar to that of the VHDL xe2x80x9cgenerate loopxe2x80x9d. However, xe2x80x9cfor loopsxe2x80x9d and xe2x80x9cgenerate loopsxe2x80x9d can be burdensome and inefficient to code. In addition, when xe2x80x9cfor loopsxe2x80x9d and xe2x80x9cgenerate loopsxe2x80x9d are used in preprocessing to generate the instances and connections, but the connection specification still has to be checked against the modules being connected to assure that the preprocessing was specified successfully. This is because the interconnect module signals are not developed from the modules being interconnected. Instead, the interconnection module signal specification is checked against the modules being interconnected. This leads to potential errors that can reduce the efficiency of the coding of the interconnection.
It is generally recognized as good hardware design practice to use the same signal name in a receiving module as in a transmitting module (see for example, M. Keating and P. Bricaud, xe2x80x9cReuse Methodology Manualxe2x80x9d, Kluwar Academic Publishers, 1999. ). For example, if the clock signal name in the design for a clock-generating module is xe2x80x9cCKxe2x80x9d, use of xe2x80x9cCKxe2x80x9d as the signal name for the corresponding nets on modules that receive that clock signal makes the net function clear to anyone reading the design description. This accepted practice has prompted many designers to develop a program that automatically generates a module that interconnects sub-modules. Designers in many development labs have turned to preprocessors, outside of the standard HDLs (Verilog or VHDL) language definition, to automatically generate interconnect HDL modules. These preprocessors are generally written in the PERL language, and may invoke PERL""s support of regular expression matching. They often combine input-output port naming of the interconnected sub-modules with rules supplied from another file.
The present invention relates generally to a regular expression support for hardware description languages and methods therefor. Objects, advantages and features of the invention will become apparent to those skilled in the art upon consideration of the following detailed description of the invention.
In accordance with an exemplary embodiment, a method consistent with the invention of iterating instances and connections in a Hardware Description Language include: receiving hardware description language (HDL) code with embedded regular expressions to define instances and interconnections of a module; identifying the regular expressions within the code; and elaborating the instances and interconnections of the module based upon the regular expressions.
Another method of iterating instances and interconnections in a hardware description language consistent with an embodiment of the invention includes: providing Hardware Description Language (HDL) code using regular expressions to define instances and interconnections of a module; and instantiation and interconnection processing the HDL code by: analyzing the code to identify the regular expressions; applying HDL grammar rules to the code; generating a data structure corresponding to the module defined by the code; elaborating the data structure into instances and interconnections of the module defined by the regular expressions in the code; and generating HDL compliant text by traversing the instances and interconnections of the elaborated data structure and translating each instance and interconnection into HDL compliant text.
A computer system for processing Hardware Description Language (HDL) code consistent with embodiments of the invention includes a processor. An input circuit coupled to the processor receives HDL code having embedded regular expression descriptions of instances and interconnections. A storage arrangement is coupled to the processor for storing computer programs and data. A program receives the HDL code and elaborates the HDL code into explicit instances and interconnections describing a selected element of hardware.
In another embodiment consistent with the invention, an electronic storage medium stores instructions which, when executed on a programmed processor, carry out a process of iterating instances and interconnections in a Hardware Description Language (HDL) including: receiving Hardware Description Language code with embedded regular expressions to define instances and interconnections of a module; identifying the regular expressions within the code; and elaborating the instances and interconnections of the module based upon the regular expressions.
A method of describing a module in a Hardware Description Language (HDL) includes: providing a module name using HDL code; creating port descriptions for a port on the module using the HDL code; describing instantiation and interconnection of the module using regular expressions within the HDL code; and elaborating the module according to the regular expressions describing the instantiation and interconnection.
Many variations, equivalents and permutations of these illustrative exemplary embodiments of the invention will occur to those skilled in the art upon consideration of the description that follows. The particular examples above should not be considered to define the scope of the invention.